آی سی CEPT frame synchronization BT8510
آی

آی سی CEPT frame synchronization BT8510

نو

شماره کالا: 34801105

900٬000 تومان

10 عدد از این کالا موجود است

توضیحات بیشتر

Features and Modes of Operation

 This specification describes the Bt8510 El(often called CEPT or DS1A) frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include digital cross-connect systems, digital loop concentrators, DCME equipment, cus-tomer premise multiplexers, network managers, and PBXs. The circuit operates with Integrated Services Digital Network(ISDN) primary rate digital streams operating at a data rate of 2.048 Mb/s according to ITU-T Recommendation G.703.The El framer is designed to meet the basic requirements of TU-T Recom-mendation G.704. It can be used in the development of equipment to conform with ITU-T G.703($6),G.704($ 2.3 and $ 3.3),G.705($ 3),G.706,G.732, G.735,G.736,G.737,G.761, and G.823(jitter tolerance).The physical line interface is included on-chip, accommodating both 75 ohm and 120ohm cables. Data and clock can be recovered from received signals with up to-12dB(120ohm cables) and-15 dB(75 ohm cables) of attenuation. The analog circuits in the physical line interface may be powered-down if unused.Digital logic-level inputs and outputs are also provided for this case.For ISDN applications, additional functions are provided to meet the require-ments of ITU-TI.431,I.604 and G.962. These functions include LAPD format-ting in Time Slot 16(TS16), full access to the Sa bits on a multiframe basis, line loopback, per-DS0 loopbacks, idle code word insertion, and comprehensive CRC-4functions.An off-line framer is provided in the receiver. The framer has an average reframe time to the Frame Alignment Signal (FAS) of about 1 ms. Separate multi-frame synchronization circuits are provided in the receiver for recovery ofreceived Channel Associated Signaling(CAS) and the CRC-4 multiframe signals.CRC-4 error checking is performed and Far-End Block Error (FEBE) bits are transmitted in accordance with G.706 if these modes are enabled.Through an 8-bit parallel interface, an external microprocessor or microcon-troller can monitor all status conditions, provide configuration control, and access signaling and PCM data. The processor interface uses a multiplexed address/data bus, and can be directly connected to Intel 8051 and Motorola 68HC11 microcon-trollers, without glue logic.